View X98027L128-33-Z_1132727.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X98027
Data Sheet May 26, 2005 FN8221.0
275MHz Triple Video Digitizer with Digital PLL
The X98027 3-channel, 8-bit Analog Front End (AFE) contains all the components necessary to digitize analog RGB or YUV graphics signals from personal computers, workstations and video set-top boxes. The fully differential analog design provides high PSRR and dynamic performance to meet the stringent requirements of the graphics display industry. The AFE's 275MSPS conversion rate supports resolutions up to QXGA at 60Hz refresh rate, while the front end's high input bandwidth ensures sharp images at the highest resolutions. To minimize noise, the X98027's analog section features 2 sets of pseudo-differential RGB inputs with programmable input bandwidth, as well as internal DC restore clamping (including mid-scale clamping for YUV signals). This is followed by the programmable gain/offset stage and the three 275MSPS Analog-to-Digital Converters (ADCs). Automatic Black Level Compensation (ABLCTM) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The X98027's digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 275MHz with sampling clock jitter of 250ps peak to peak.
Features
* 275MSPS maximum conversion rate * Low PLL clock jitter (250ps p-p @ 275MSPS) * 64 interpixel sampling positions * 0.35Vp-p to 1.4Vp-p video input range * Programmable bandwidth (100MHz to 780MHz) * 2 channel input multiplexer * RGB and YUV 4:2:2 output formats * 5 embedded voltage regulators allow operation from single 3.3V supply and enhance performance, isolation * Completely independent 8 bit gain/10 bit offset control * CSYNC and SOG support * Trilevel sync detection * 1.2W typical PD @ 275MSPS * Pb-free plus anneal available (RoHS compliant)
Applications
* LCD Monitors and Projectors * Digital TVs * Plasma Display Panels * RGB Graphics Processing * Scan Converters
Simplified Block Diagram
Offset DAC ABLCTM
Voltage Clamp RGB/YPbPrIN 1 RGB/YPbPrIN 2 3 3 PGA +
8 or 16 8 bit ADC x3 RGB/YUVOUT HSYNCOUT VSYNCOUT
SOGIN1/2 HSYNCIN1/2 VSYNCIN1/2
Sync Processing
Digital PLL
HSOUT PIXELCLKOUT
AFE Configuration and Control
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X98027
Ordering Information
PART NUMBER X98027L128-3.3 X98027L128-3.3-Z (See Note) MAXIMUM PIXEL RATE 275MHz 275MHz TEMP RANGE (C) 0 to 70 0 to 70 PACKAGE 128 MQFP 128 MQFP (Pb-free) PART MARKING X98027L-3.3 X98027L-3.3Z
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
VCLAMP Offset DAC 10
ABLCTM
RIN1
VIN+ VIN-
8
PGA
VCLAMP
RIN2
+
8 bit ADC
8 8
RP[7:0] RS[7:0]
Offset DAC
10
ABLCTM
VIN+ VIN-
Output Data Formatter
GIN1 RGBGND1 GIN2 RGBGND2
8 8
PGA
VCLAMP
+
8 bit ADC
8
GP[7:0] GS[7:0]
Offset DAC
10
ABLCTM
BIN1
VIN+ VIN-
8 8
PGA
BIN2
+
8 bit ADC
8
BP[7:0] BS[7:0]
DATACLK SOGIN1 SOGIN2 HSYNCIN1 HSYNCIN2 VSYNCIN1 VSYNCIN2 HSYNCOUT CLOCKINV XTALIN XTALOUT SCL SDA SADDR VSYNCOUT DATACLK
Sync Processing
AFE Configuration and Control
HSOUT VSOUT
Digital PLL Serial Interface
XTALCLKOUT
2
FN8221.0 May 26, 2005
X98027
Absolute Maximum Ratings
Voltage on VA, VD, or VX (referenced to GNDA=GNDD=GNDX) . . . . . . . . . . . . . . . . . . . 4.0V Voltage on any analog input pin (referenced to GNDA) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VA Voltage on any digital input pin (referenced to GNDD) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Operating Temperature range . . . . . . . . . . . . . . . . . . . . . 0C to +70C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . VA = VD = VX = 3.3V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications
SYMBOL
T
Specifications apply for VA = VD = VX = 3.3V, pixel rate = 275MHz, fXTAL = 25MHz, TA = 25C, unless otherwise noted COMMENT MIN TYP MAX UNIT
PARAMETER
FULL CHANNEL CHARACTERISTICS ADC Resolution Missing Codes Conversion Rate DNL INL Differential Non-Linearity Integral Non-Linearity Gain Adjustment Range Gain Adjustment Resolution Gain Matching Between Channels Percent of full scale Guaranteed monotonic Per Channel 10 0.7 1.6 6 8 1 0.125 127 5 0.5 8 None 275 +1.2 -0.9 3.75 MHz LSB LSB dB Bits % LSB LSB ns Bits
Full Channel Offset Error, ABLCTM enabled ADC LSBs, over time and temperature Offset Adjustment Range, ABLCTM enabled or disabled Overvoltage Recovery Time ADC LSBs (see ABLCTM applications information section) For 150% overrange, maximum bandwidth setting
ANALOG VIDEO INPUT CHARACTERISTICS (RIN1, GIN1, BIN1, RIN2, GIN2, BIN2) Input Range Input Bias Current Input Capacitance Full Power Bandwidth INPUT CHARACTERISTICS (SOGIN1, SOGIN2) VIH/VIL Input Threshold Voltage Hysteresis Input capacitance INPUT CHARACTERISTICS (HSYNCIN1, HSYNCIN2) VIH/VIL Input Threshold Voltage Hysteresis RIN Input impedance Input capacitance Programmable - See Register Listing for Details Centered around threshold voltage 0.4 to 3.2 240 1.2 5 V mV k pF Programmable - See Register Listing for Details Centered around threshold voltage 0 to -0.3 40 5 V mV pF Programmable DC restore clamp off 0.35 0.7 0.01 5 780 1.4 1 VP-P A pF MHz
3
FN8221.0 May 26, 2005
X98027
Electrical Specifications
SYMBOL Specifications apply for VA = VD = VX = 3.3V, pixel rate = 275MHz, fXTAL = 25MHz, TA = 25C, unless otherwise noted (Continued) COMMENT MIN TYP MAX UNIT
PARAMETER
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINVIN, RESET) VIH VIL I Input HIGH Voltage Input LOW Voltage Input leakage current Input capacitance SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNCIN1, VSYNCIN2) VT + VTI Low to High Threshold Voltage High to Low Threshold Voltage Input leakage current Input capacitance DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK) VOH VOL Output HIGH Voltage, IO = 16mA Output LOW Voltage, IO = -16mA 2.4 0.4 V V 10 5 1.45 0.95 V V nA pF RESET has a 70k pullup to VD 10 5 2.0 0.8 V V nA pF
DIGITAL OUTPUT CHARACTERISTICS (RP, GP, BP, RS, GS, BS, HSOUT, VSOUT, HSYNCOUT, VSYNCOUT) VOH VOL RTRI Output HIGH Voltage, IO = 8mA Output LOW Voltage, IO = -8mA Pulldown to GNDD when three-state RP, GP, BP, RS, GS, BS only 58 2.4 0.4 V V k
DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLKOUT) VOH VOL Output HIGH Voltage, IO = 4mA Output LOW Voltage, IO = -4mA XTALCLKOUT only; SDA is open-drain 2.4 0.4 V V
POWER SUPPLY REQUIREMENTS VA VD VX IA ID IX PD Analog Supply Voltage Digital Supply Voltage Crystal Oscillator Supply Voltage Analog Supply Current Digital Supply Current Crystal Oscillator Supply Current Total Power Dissipation Operating (average) Power-down Mode JA Thermal Resistance, Junction to Ambient Operating Operating (grayscale) 3 3 3 3.3 3.3 3.3 190 170 0.7 1.2 50 30 3.6 3.6 3.6 200 180 2 1.4 80 V V V mA mA mA W mW C/W
AC TIMING CHARACTERISTICS PLL Jitter Sampling Phase Steps Sampling Phase Tempco Sampling Phase Differential Nonlinearity HSYNC Frequency Range fXTAL tSETUP Crystal Frequency Range DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) Degrees out of 360 10 23 (Note 2) 1.3 25 5.6 per step 64 1 3 150 27 ps/C kHz MHz ns 250 450 ps p-p
4
FN8221.0 May 26, 2005
X98027
Electrical Specifications
SYMBOL tHOLD Specifications apply for VA = VD = VX = 3.3V, pixel rate = 275MHz, fXTAL = 25MHz, TA = 25C, unless otherwise noted (Continued) COMMENT 15pF DATACLK load, 15pF DATA load (Note 1) MIN 2.0 TYP MAX UNIT ns
PARAMETER DATA valid after rising edge of DATACLK
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE) fSCL SCL Clock Frequency Maximum width of a glitch on SCL that will be suppressed tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH NOTES: 1. Setup and hold times are at a 140MHz DATACLK rate. 2. See Table 8 on page 24. SCL LOW to SDA Data Out Valid Time the bus must be free before a new transmission can start Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time 4 XTAL periods min 2 XTAL periods min 5 XTAL periods plus SDA's RC time constant 1.3 1.3 0.6 0.6 0.6 100 0 0.6 160 0 80 See comment 400 kHz ns s s s s s s ns ns s ns
tF SCL tSU:ST SDA IN tHD:STA tSU:DAT
tHIGH
tLOW
tR
tHD:DAT
tSU:STO
tAA SDA OUT
tDH
tBUF
FIGURE 1. 2 WIRE INTERFACE TIMING
DATACLK
DATACLK tSETUP Pixel Data tHOLD
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
5
FN8221.0 May 26, 2005
X98027
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
HSYNC IN
DATACLK 8.5 DATACLK Pipeline Latency R P/G P/B P[7:0] D0 D1 D2 D3
R S/G S/B S[7:0]
HSOUT
Programmable Width and Polarity
FIGURE 3. 24 BIT OUTPUT MODE
HSYNC IN
Th HSYNC d ( bl l di t ili ) th t th DPLL i l k d t The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
DATACLK 8.5 DATACLK Pipeline Latency GP[7:0] G 0 (Y o) G 1 (Y1) G 2 (Y2)
RP[7:0]
B0 (U o)
R1 (V 1)
B2 (U 2)
BP[7:0]
HSOUT
Programmable Width and Polarity
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
6
FN8221.0 May 26, 2005
X98027
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
HSYNCIN
DATACLK
RP/GP/BP[7:0]
D0
D2
RS/GS/BS[7:0]
D1
D3
HSOUT
Programmable Width and Polarity
FIGURE 5. 48 BIT OUTPUT MODE
HSYNC
HSYNCIN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
Analog Video In
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
DATACLK
RP/GP/BP[7:0]
D0
D2
RS/GS/BS[7:0]
D1
HSOUT
Programmable Width and Polarity
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
7
FN8221.0 May 26, 2005
X98027 Pinout
X98027 (128-PIN MQFP) TOP VIEW
V S Y NC OUT HS Y NC OUT DAT AC LK DAT AC LK
HS OUT
V S OUT
V C OR E
G ND D
G ND D
G ND D
G ND D
R P0
R P1
R P2
R P3
R P4
R P5
R P6
R P7
RS0
RS1
RS2
RS3 104
VD
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
NC NC G ND A V B Y P AS S G ND A VA R IN 1 G ND A V B Y P AS S G ND A VA G IN 1 R G B G ND 1 S OG IN 1 G ND A V B Y P AS S G ND A VA B IN 1 VA G ND A R IN 2 G ND A G IN 2 R G B G ND 2 S OG IN 2 G ND A B IN 2 VA G ND A V C OR E ADC G ND D HS Y NC IN 1 HS Y NC IN 2 VA G ND A G ND X VX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
103
RS4 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VD
RS5 RS6 RS7 VD G ND D GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 VD G ND D GS0 GS1 GS2 GS3 GS4 GS5 GS6 GS7 V C OR E G ND D VD G ND D BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 VD G ND D V R E G IN
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63 NC
V S Y NC IN 1
V S Y NC IN 2
BS7
BS6
BS5
BS4
BS3
BS2
BS1
G ND D
G ND D
G ND D
XT AL IN
C LOC K INV IN
V P LL
S DA
XT AL OUT
XT ALC LOC K OUT
SCL
BS0
VD
8
V R E G OUT
RESET
S ADDR
V C OR E
64
FN8221.0 May 26, 2005
X98027 Pin Descriptions
SYMBOL RIN1 GIN1 BIN1 RGBGND1 PIN 7 12 19 13 DESCRIPTION Analog input. Red channel 1. DC couple or AC couple through 0.1F. Analog input. Green channel 1. DC couple or AC couple through 0.1F. Analog input. Blue channel 1. DC couple or AC couple through 0.1F. Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration. Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the AC-coupled configuration, but the pin should still be tied to GNDA. Analog input. Sync on Green. Connect to GIN1 through a 0.01F capacitor in series with a 500 resistor. Digital input, 5V tolerant, 240mV hysteresis, 1.2k impedance to GNDA. Connect to channel 1's HSYNC signal through a 680 series resistor. Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal. Analog input. Red channel 2. DC couple or AC couple through 0.1F. Analog input. Green channel 2. DC couple or AC couple through 0.1F. Analog input. Blue channel 2. DC couple or AC couple through 0.1F. Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration. Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the AC-coupled configuration, but the pin should still be tied to GNDA. Analog input. Sync on Green. Connect to GIN1 through a 0.01F capacitor in series with a 500 resistor. Digital input, 5V tolerant, 240mV hysteresis, 1.2k impedance to GNDA. Connect to channel 2's HSYNC signal through a 680 series resistor. Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal. Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to DGND if unused. Digital input, 5V tolerant, active low, 70k pull-up to VD. Take low for at least 1s and then high again to reset the X98027. This pin is not necessary for normal use and may be tied directly to the VD supply. Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. 3.3V digital output. Buffered crystal clock output at fXTAL or fXTAL/2. May be used as system clock for other system components. Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A including R/W bit) when tied high. Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface. Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface. 3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated. 3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated. 3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated. 3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated. 3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated. 3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated. 3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48 bit mode. 3.3V digital output. Inverse of DATACLK.
SOGIN1 HSYNCIN1 VSYNCIN1 RIN2 GIN2 BIN2 RGBGND2
14 33 44 22 24 28 25
SOGIN2 HSYNCIN2 VSYNCIN2 CLOCKINVIN
26 34 45 41
RESET XTALIN XTALOUT XTALCLKOUT SADDR SCL SDA RP[7:0] RS[7:0] GP[7:0] GS[7:0] BP[7:0] BS[7:0] DATACLK DATACLK
46 39 40 47 48 50 49 112-119 100-107 90-97 80-87 68-75 55-62 121 122
9
FN8221.0 May 26, 2005
X98027 Pin Descriptions (Continued)
SYMBOL HSOUT VSOUT HSYNCOUT PIN 125 126 127 DESCRIPTION 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals) 3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after the trailing edge of HSOUT. This signal is usually not needed - use VSYNCOUT as VSYNC source. 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC period. HSOUT should be used to detect the beginning of a line. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or SOGIN. 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a frame and measure the VSYNC period. Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1F. Ground return for VA and VBYPASS.
VSYNCOUT
128
VA GNDA
6, 11, 18, 20, 29, 35 3, 5, 8, 10, 15, 17, 21, 23, 27, 30, 36 54, 67, 77, 89, 99, 111, 124 32, 43, 51, 53, 66, 76, 78, 88, 98, 108, 110, 120, 123 38 37 4, 9, 16 65 64
VD GNDD
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1F. Ground return for VD, VCORE, VCOREADC, and VPLL.
VX GNDX VBYPASS VREGIN VREGOUT
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1F. Ground return for VX. Bypass these pins to GNDA with 0.1F. Do not connect these pins to each other or anything else. 3.3V input voltage for VCORE voltage regulator. Connect to a 3.3V source, and bypass to GNDD with 0.1F. Regulated output voltage for VPLL, VCOREADC and VCORE; typically 1.9V. Connect only to VPLL, VCOREADC and VCORE and bypass at input pins as instructed below. Do not connect to anything else - this output can only supply power to VPLL, VCOREADC and VCORE. Internal power for the ADC's digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD with 0.1F. Internal power for the PLL's digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD with 0.1F. Internal power for core logic. Connect to VREGOUT and bypass each pin to GNDD with 0.1F. Reserved. Do not connect anything to these pins.
VCOREADC VPLL VCORE NC
31 42 52, 79, 109 1, 2, 63
10
FN8221.0 May 26, 2005
X98027 Register Listing
ADDRESS 0x01 REGISTER (DEFAULT VALUE) SYNC Status (read only) BIT(s) 0 1 2 3 4 5 6 7 0x02 SYNC Polarity (read only) 0 1 2 3 4 5 7:6 0x03 HSYNC Slicer (0x44) 2:0 FUNCTION NAME HSYNC1 Active HSYNC2 Active VSYNC1 Active VSYNC2 Active SOG1 Active SOG2 Active PLL Locked CSYNC Detected at Sync Splitter Output HSYNC1 Polarity HSYNC2 Polarity VSYNC1 Polarity VSYNC2 Polarity HSYNC1 Trilevel HSYNC2 Trilevel N/A HSYNC1 Threshold DESCRIPTION 0: HSYNC1 is Inactive 1: HSYNC1 is Active 0: HSYNC2 is Inactive 1: HSYNC2 is Active 0: VSYNC1 is Inactive 1: VSYNC1 is Active 0: VSYNC2 is Inactive 1: VSYNC2 is Active 0: SOG1 is Inactive 1: SOG1 is Active 0: SOG2 is Inactive 1: SOG2 is Active 0: PLL is unlocked 1: PLL is locked to incoming HSYNC 0: Composite Sync signal not detected 1: Composite Sync signal is detected 0: HSYNC1 is Active High 1: HSYNC1 is Active Low 0: HSYNC2 is Active High 1: HSYNC2 is Active Low 0: VSYNC1 is Active High 1: VSYNC1 is Active Low 0: VSYNC2 is Active High 1: VSYNC2 is Active Low 0: HSYNC1 is Standard Sync 1: HSYNC1 is Trilevel Sync 0: HSYNC2 is Standard Sync 1: HSYNC2 is Trilevel Sync Returns 0 000 = lowest (0.4V) All values referred to 100 = default (2.0V) voltage at HSYNC input 111 = highest (3.2V) pin, 240mV hysteresis Set to 00 See HSYNC1 0: HSYNC/VSYNC Digital Glitch Filter Enabled (default) 1: HSYNC/VSYNC Digital Glitch Filter Disabled 0x0 = lowest (0mV) 40mV hysteresis at 0x8 = default (160mV) all settings 0xF = highest (300mV) 20mV step size 0: SOG low pass filter disabled (default) 1: SOG low pass filter enabled, 14MHz corner 0: 40mV SOG hysteresis enabled 1: 40mV SOG hysteresis disabled (default) Set to 00.
3 6:4 7 0x04 SOG Slicer (0x08) 3:0
Reserved HSYNC2 Threshold Disable Glitch Filter SOG1 and SOG2 Threshold SOG Filter Enable SOG Hysteresis Disable Reserved
4 5 7:6
11
FN8221.0 May 26, 2005
X98027 Register Listing (Continued)
ADDRESS 0x05 REGISTER (DEFAULT VALUE) Input configuration (0x00) BIT(s) 0 1 FUNCTION NAME Channel Select Input Coupling 0: VGA1 1: VGA2 0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) 1: DC coupled (+ and - inputs are brought to pads and never connected to clamp DACs). Analog clamp signal is turned off in this mode. 2 RGB/YUV 0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale analog shift for R, G, and B, base ABLCTM target code = 0x00 for R, G, and B) 1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for G, half scale analog shift for G channel only, base ABLCTM target code = 0x00 for G, = 0x80 for R and B) 3 4 Sync Type Composite Sync Source 0: Separate HSYNC/VSYNC 1: Composite (from SOG or CSYNC on HSYNC) 0: SOGIN 1: HSYNCIN Note: If Sync Type = 0, the multiplexer will pass HSYNCIN regardless of the state of this bit. 0: DC restore clamping and ABLCTM suspended during COAST 1: DC restore clamping and ABLCTM continue during COAST Set to 00. Channel gain, where: gain (V/V) = 0.5 + [7:0]/170 0x00: gain = 0.5 V/V (1.4VP-P input = full range of ADC) 0x55: gain = 1.0 V/V (0.7VP-P input = full range of ADC) 0xFF: gain = 2.0 V/V (0.35VP-P input = full range of ADC) 0x09 0x0A 0x0B Red Offset (0x80) Green Offset (0x80) Blue Offset (0x80) 7:0 7:0 7:0 Red Offset Green Offset Blue Offset ABLCTM enabled: digital offset control. A 1 LSB change in this register will shift the ADC output by 1 LSB. ABLCTM disabled: analog offset control. These bits go to the upper 8 bits of the 10 bit offset DAC. A 1LSB change in this register will shift the ADC output approximately 1 LSB (Offset DAC range = 0) or 0.5LSBs (Offset DAC range = 1). 0x00 = min DAC value or -0x80 digital offset, 0x80 = mid DAC value or 0x00 digital offset, 0xFF = max DAC value or +0x7F digital offset 0: 1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB) 1: 1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB) Set to 0. DESCRIPTION
5
COAST CLAMP enable Reserved Red Gain
7:6 0x06 Red Gain (0x55) 7:0
0x07
Green Gain (0x55)
7:0
Green Gain
0x08
Blue Gain (0x55)
7:0
Blue Gain
0x0C
Offset DAC Configuration (0x00)
0 1 3:2 5:4 7:6
Offset DAC Range Reserved
Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset DAC control. Green Offset DAC Combine with their respective MSBs in registers 0x09, 0x0A, LSBs and 0x0B to achieve 10 bit offset DAC control. Blue Offset DAC LSBs
12
FN8221.0 May 26, 2005
X98027 Register Listing (Continued)
ADDRESS 0x0D REGISTER (DEFAULT VALUE) AFE Bandwidth (0x0E) BIT(s) 0 3:1 FUNCTION NAME Unused AFE BW Value doesn't matter 3dB point for AFE lowpass filter 000: 100MHz 111: 780MHz (default) 0000: Disabled (default) See Bandwidth and Peaking Control section for more information 14 bit HTOTAL (number of active pixels) value The minimum HTOTAL value supported is 0x200. HTOTAL to PLL is updated on LSB write only. Used to control the phase of the ADC's sample point relative to the period of a pixel. Adjust to obtain optimum image quality. One step = 5.625 (1.56% of pixel period). Number of lines the PLL will coast prior to the start of VSYNC. Applies only to internally generated COAST signals. Number of lines the PLL will coast after the end of VSYNC. Applies only to internally generated COAST signals. 0: Lock on trailing edge of HSYNC1 (default) 1: Lock on leading edge of HSYNC1 0: Lock on trailing edge of HSYNC2 (default) 1: Lock on leading edge of HSYNC2 Set to 0. 0: CLKINVIN pin enabled (default) 1: CLKINVIN pin disabled (internally forced low) 00: CLKINV (default) 01: External CLAMP (see Note) 10: External COAST 11: External PIXCLK Note: the CLAMP pulse is used to - perform a DC restore (if enabled) - start the ABLCTM function (if enabled), and - update the data to the Offset DACs (always). When in the default internal CLAMP mode, the X98027 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values will only change on the leading edge of CLAMP. If there is no internal clamp signal, there will be up to a 100ms delay between when the PGA gain or offset DAC register is written to, and when the PGA or offset DAC is actually updated. 6 7 0x14 DC Restore and ABLCTM starting pixel MSB (0x00) DC Restore and ABLCTM starting pixel LSB (0x00) DC Restore Clamp Width (0x10) 4:0 XTALCLKOUT Frequency Disable XTALCLKOUT DC Restore and ABLCTM starting pixel (MSB) DC Restore and ABLCTM starting pixel (LSB) DC Restore clamp width (pixels) 0: XTALCLKOUT= fCRYSTAL (default) 1: XTALCLKOUT= fCRYSTAL/2 0 = XTALCLKOUT enabled 1 = XTALCLKOUT is logic low Pixel after HSYNCIN trailing edge to begin DC restore and ABLCTM functions. 13 bits. Set this register to the first stable black pixel following the trailing edge of HSYNCIN. DESCRIPTION
7:4 0x0E 0x0F 0x10 PLL Htotal MSB (0x03) PLL Htotal LSB (0x20) PLL Sampling Phase (0x00) 5:0 7:0 5:0
Peaking PLL Htotal MSB PLL Htotal LSB PLL Sampling Phase
0x11
PLL Pre-coast (0x08)
7:0
Pre-coast
0x12 0x13
PLL Post-coast (0x00) PLL Misc (0x00)
7:0 0 1 2 3 5:4
Post-coast PLL Lock Edge HSYNC1 PLL Lock Edge HSYNC2 Reserved CLKINVIN Pin Disable CLKINVIN Pin Function
0x15
7:0
0x16
7:0
Width of DC restore clamp used in AC-coupled configurations. Has no effect on ABLCTM. Minimum value is 0x02 (a setting of 0x01 or 0x00 will not generate a clamp pulse).
13
FN8221.0 May 26, 2005
X98027 Register Listing (Continued)
ADDRESS 0x17 REGISTER (DEFAULT VALUE) ABLCTM Configuration (0x40) BIT(s) 0 1 3:2 FUNCTION NAME ABLCTM disable Reserved ABLCTM pixel width DESCRIPTION 0: ABLCTM enabled (default) 1: ABLCTM disabled Set to 0. Number of black pixels averaged every line for ABLCTM function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels ABLCTM Time constant (lines) = 2(5+[6:4]) 000 = 32 lines 100 = 256 lines (default) 111 = 4096 lines Set to 0. 0: 24 bits: Data output on RP, GP, BP only; RS, GS, BS are all driven low (default) 1: 48 bits: Data output on RP, GP, BP, RS, GS, BS 0: No interleaving: data changes on same edge of DATACLK (default) 1: Interleaved: Secondary databus data changes on opposite edge of DATACLK from primary databus 0: First data byte after trailing edge of HSOUT appears on RP, GP, BP (default) 1: First data byte after trailing edge of HSOUT appears on RS, GS, BS (primary and secondary busses are reversed) Set to 0. 0: Data is formatted as 4:4:4 (RGB, default) 1: Data is decimated to 4:2:2 (YUV), blue channel is driven low 0: HSOUT, VSOUT, and Pixel Data change on falling edge of DATACLK (default) 1: HSOUT, VSOUT, and Pixel Data change on rising edge of DATACLK 0: Active High (default) 1: Active Low 0: Active High (default) 1: Active Low HSOUT width, in pixels. Minimum value is 0x01 for 24 bit modes, 0x02 for 48 bit modes. 0 = Output byte enabled 1 = Output byte three-stated These bits override all other I/O settings Output data pins have 58k pulldown resistors to GNDD.
6:4
ABLCTM bandwidth
7 0x18 Output Format (0x00) 0
Reserved Bus Width
1
Interleaving (48 bit mode only)
2
Bus Swap (48 bit mode only)
3 4
Reserved 422 (24 bit mode only) DATACLK Polarity
5
6 7 0x19 0x1A HSOUT Width (0x10) Output Signal Disable (0x00) 7:0 0 1 2 3 4 5 6 7
VSOUT Polarity HSOUT Polarity HSOUT Width Three-state RP[7:0] Three-state RS[7:0] Three-state GP[7:0] Three-state GS[7:0] Three-state BP[7:0] Three-state BS[7:0] Three-state DATACLK Three-state DATACLK
0 = DATACLK enabled 1 = DATACLK three-stated 0 = DATACLK enabled 1 = DATACLK three-stated
14
FN8221.0 May 26, 2005
X98027 Register Listing (Continued)
ADDRESS 0x1B REGISTER (DEFAULT VALUE) Power Control (0x00) BIT(s) 0 1 2 3 7:4 0x1C 0x23 Reserved (0x47) DC Restore Clamp (0x08) 7:0 3:0 6:4 FUNCTION NAME Red Power-down Green Power-down Blue Power-down PLL Power-down Reserved Reserved Reserved DC Restore Clamp Impedance DESCRIPTION 0 = Red ADC operational (default) 1 = Red ADC powered down 0 = Green ADC operational (default) 1 = Green ADC powered down 0 = Blue ADC operational (default) 1 = Blue ADC powered down 0 = PLL operational (default) 1 = PLL powered down Set to 0 Set to 0x49 for best performance with NTSC and PAL video Set to 1000 DC Restore clamp's ON resistance. Shared for all three channels 0: Infinite (clamp disconnected) (default) 1: 1600 2: 800 3: 533 4: 400 5: 320 6: 267 7: 228 Set to 0
7
Reserved
0x2B
Crystal Compensation (0x14)
7:0
XTALCOMP
See Table 8 on page 25. The X98027's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point. The crystal-locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. An intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10MHz or higher) to QXGA 60Hz (275MHz). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals.
Technical Highlights
The X98027 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically this function has been implemented as a traditional analog PLL. At SXGA and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). As display resolutions and refresh rates have increased, however, the pixel period has decreased. An XGA pixel at a 60Hz refresh rate has 15.4ns to change and settle to its new value. But at UXGA 75Hz, the pixel period is 4.9ns. Most consumer graphics cards spend most of that time slewing to the new pixel value. The pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. In many cases it never settles at all. So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet.
Automatic Black Level Compensation (ABLCTM) and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC, to both correct for offsets on the incoming video signals and add/subtract an offset for user "brightness control". This solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then servos the offset DACs until that offset is nulled (or produces the desired ADC output code). Once this has been accomplished, the offset (both the offset in the AFE and the offset of the video card generating the signal) is subject to drift - the temperature inside a monitor or projector can
FN8221.0 May 26, 2005
15
X98027
easily change 50C between power-on/offset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment have reached steady state. Offset can drift significantly over 50C, reducing image quality and requiring that the user do a manual calibration once the monitor has warmed up. In addition to drift, many AFEs exhibit interaction between the offset and gain controls. When the gain is changed, the magnitude of the offset is changed as well. This again increases the complexity of the firmware as it tries to optimize gain and offset settings for a given video input signal. Instead of adjusting just the offset, then the gain, both have to be adjusted interactively until the desired ADC output is reached. The X98027 simplifies offset and gain adjustment and completely eliminates offset drift using its Automatic Black Level Compensation (ABLCTM) function. ABLCTM monitors the black level and continuously adjusts the X98027's 10 bit offset DACs to null out the offset. Any offset, whether due to the video source or the X98027's analog amplifiers, is eliminated with 10 bit (1/4 of an 8 bit ADC LSB) accuracy. Any drift is compensated for well before it can have a visible effect. Manual offset adjustment control is still available - an 8 bit register allows the firmware to adjust the offset 64 codes in exactly 1 ADC LSB increments. And gain is now completely independent of offset - adjusting the gain no longer affects the offset, so there is no longer a need to program the firmware to cope with interactive offset and gain controls. Finally, there should be no concerns over ABLCTM itself introducing visible artifacts; it doesn't. ABLCTM operates at a very low frequency, changing the offset in 1/4 LSB increments, so it doesn't cause visible brightness fluctuations. And once ABLCTM is locked, if the offset doesn't drift, the DACs won't change. If desired, ABLCTM can be disabled, allowing the firmware to work in the traditional way, with 10 bit offset DACs under the firmware's control.
Functional Description
Inputs
The X98027 digitizes analog video inputs in both RGB and Component (YPbPr) formats, with or without embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal to 0V. The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals.
Component YUV Inputs
In addition to RGB and RGB with SOG, the X98027 has an option that is compatible with the component YPbPr and YCbCr video inputs typically generated by DVD players. While the X98027 digitizes signals in these color spaces, it does not perform color space conversion; if it digitizes an RGB signal, it outputs digital RGB, while if it digitizes a YPbPr signal, it outputs digital YPbPr. For simplicity's sake we will call these non-RGB signals YUV. The Luminance (Y) signal is applied to the Green Channel and is processed in a manner identical to the Green input with SOG described previously. The color difference signals U and V are bipolar and swing both above and below the black level. When the YUV mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x80. Setting configuration register 0x05[2] = 1 enables the YUV signal processing mode of operation.
TABLE 1. YUV MAPPING (4:4:4) INPUT SIGNAL Y U V X98027 INPUT CHANNEL Green Blue Red X98027 OUTPUT ASSIGNMENT Green Blue Red OUTPUT SIGNAL Y0Y1Y2Y3 U0U1U2U3 V0V1V2V3
Gain and Offset Control
To simplify image optimization algorithms, the X98027 features fully-independent gain and offset adjustment. Changing the gain does not affect the DC offset, and the weight of an Offset DAC LSB does not vary depending on the gain setting. The full-scale gain is set in the three 8-bit registers (0x060x08). The X98027 can accept input signals with amplitudes ranging from 0.35VP-P to 1.4VP-P. The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x80, which forces the ADC to output code 0x00 (or 0x80 for U and V channels in YUV mode) during the back porch period when ABLCTM is enabled. 16
The X98027 can optionally decimate the incoming data to provide a 4:2:2 output stream (configuration register 0x18[4] = 1) as shown in Table 2.
TABLE 2. YUV MAPPING (4:2:2) INPUT SIGNAL Y U V X98027 INPUT CHANNEL Green Blue Red X98027 OUTPUT ASSIGNMENT Green Blue Red OUTPUT SIGNAL Y0Y1Y2Y3 driven low U0V1U2V3
FN8221.0 May 26, 2005
X98027
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled (see register 0x05[1]). AC coupling is usually preferred since it allows video signals with substantial DC offsets to be accurately digitized. The X98027 provides a complete internal DC-restore function, including the DC restore clamp (See Figure 7) and programmable clamp timing (registers 0x14, 0x15, 0x16, and 0x23). When AC-coupled, the DC restore clamp is applied every line, a programmable number of pixels after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the clamp will not be applied while the DPLL is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or Macrovision signals. After the trailing edge of HSYNC, the DC restore clamp is turned on after the number of pixels specified in the DC Restore and ABLCTM Starting Pixel registers (0x14 and 0x15) has been reached. The clamp is applied for the number of pixels specified by the DC Restore Clamp Width Register (0x16). The clamp can be applied to the back porch of the video, or to the front porch (by increasing the DC Restore and ABLCTM Starting Pixel registers so all the active video pixels are skipped). If DC-coupled operation is desired, the input to the ADC will be the difference between the input signal (RIN1, for example) and that channel's ground reference (RGBGND1 in that example).
SOG
For component YUV signals, the sync signal is embedded on the Y channel's video, which is connected to the green input, hence the name SOG (Sync on Green). The horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. The sync tip level is typically 0.3V below the video black level. To minimize the loading on the green channel, the SOG input for each of the green channels should be AC-coupled to the X98027 through a series combination of a 10nF capacitor and a 500 resistor. Inside the X98027, a window comparator compares the SOG signal with an internal 4 bit programmable threshold level reference ranging from 0mV to 300mV below the minimum sync level. The SOG threshold level, hysteresis, and low-pass filter is programmed via register 0x04. If the Sync-On-Green function is not needed, the SOGIN pin(s) may be left unconnected.
DC Restoration
Automatic Black Level Compensation (ABLCTM) Loop
Fixed Offset Offset ADC 10 10 10 Offset Control Registers 8 ABLCTM ABLCTM Fixed Offset 0x00 8
CLAMP GENERATION DC Restore Clamp DAC VCLAMP
To ABLC Block
ABLCTM
R(GB)IN1 R(GB)GND1 R(GB)IN2 R(GB)GND2
VGA1
VIN+ VIN- PGA Input Bandwidth Bandwidth Control 8 bit ADC 8
8 8 To Output Formatter
VGA2
FIGURE 7. VIDEO FLOW (INCLUDING ABLCTM)
17
FN8221.0 May 26, 2005
X98027
ACTIVITY 0x01[6:0] & POLARITY 0x02[5:0] DETECT HSYNC1 SLICER 0x03[2:0] 0: VGA1 SOG SLICER 0x1C HSYNC2 SLICER 0x03[6:4] 1: VGA2 SOG SLICER 0x1C COAST GENERATION 0x11, 0x12, 0x13[2] HSYNCIN
HSYNCIN1
CSYNC SOURCE 00, 10, 11: HSYNCIN 0x05[4:3] 0x05[0] SOGIN 01: SOGIN VSYNCIN 0: VSYNCIN SYNC SPLITTER VSYNC SYNC TYPE 1: SYNC SPLTR 0x05[3]
HSYNCOUT
VSYNCIN1 SOGIN1
HSYNCIN2
VSYNCOUT
VSYNCIN2 SOGIN2
RP[7:0] Pixel Data from AFE 24 RS[7:0] GP[7:0]
CLOCKINVIN PLL XTALIN 0: /1 0x13 [6] /2 1: /2 0x0E through 0x13 PIXCLK XTALOUT HS
Output Formatter 0x18, 0x19, 0x1A
GS[7:0] BP[7:0] BS[7:0] DATACLK DATACLK HSOUT VSOUT XTALCLOCKOUT
FIGURE 8. SYNC FLOW
SYNC Processing
The X98027 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync-On-Green (SOG) signal embedded on the Green video input. The X98027 has SYNC activity detect functions to help the firmware determine which sync source is available.
PGA
The X98027's Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is: V GainCode Gain --- = 0.5 + --------------------------- V 170 where GainCode is the value in the Gain register for that particular color. Note that for a gain of 1 V/V for GainCode should be 85 (0x55). This is a different center value than the 128 (0x80) value used by some other AFEs, so the firmware should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per line. In normal operation this means that there is a maximum delay of one HSYNC period between a write to a Gain register for a particular color and the corresponding change in that channel's actual PGA gain. If there is no regular HSYNC/SOG source, or if the external clamp option is enabled (register 0x13[5:4]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the Gain register to update the PGA. This is not an issue in normal operation with RGB and YUV signals.
Bandwidth and Peaking Control
Register 0x0D[3:1] controls a low pass filter allowing the input bandwidth to be adjusted with three bit resolution between its default value (0x0E = 780MHz) and its minimum bandwidth (0x00, for 100MHz). Typically the higher the resolution, the higher the desired input bandwidth. To minimize noise, video signals should be digitized with the minimum bandwidth setting that passes sharp edges.
18
FN8221.0 May 26, 2005
X98027
Table 3 shows the corner frequency for different register settings.
TABLE 3. BANDWIDTH CONTROL 0x0D[3:0] VALUE (LSB = "x" = "don't care") 000x 001x 010x 011x 100x 101x 110x 111x AFE BANDWIDTH 100MHz 130MHz 150MHz 180MHz 230MHz 320MHz 480MHz 780MHz
interaction between the PGA (controlling "contrast") and the Offset DAC (controlling "brightness"). In normal operation, the Offset DAC is controlled by the ABLCTM circuit, ensuring that the offset is always reduced to sub-LSB levels (See the following ABLCTM section for more information). When ABLCTM is enabled, the Offset registers (0x09, 0x0A, 0x0B) control a digital offset added to or subtracted from the output of the ADC. This mode provides the best image quality and eliminates the need for any offset calibration. If desired, ABLCTM can be disabled (0x17[0]=1) and the Offset DAC programmed manually, with the 8 most significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least significant bits in register 0x0C[7:2]. The default Offset DAC range is 127 ADC LSBs. Setting 0x0C[0]=1 reduces the swing of the Offset DAC by 50%, making 1 Offset DAC LSB the weight of 1/8th of an ADC LSB. This provides the finest offset control and applies to both ABLCTM and manual modes.
Register 0x0D[7:4] controls a programmable zero, allowing high frequencies to be boosted, restoring some of the harmonics lost due to excessive EMI filtering, cable losses, etc. This control has a very large range, and can introduce high frequency noise into the image, so it should be used judiciously, or as an advanced user adjustment. Table 4 shows the corner frequency of the zero for different peaking register settings.
TABLE 4. PEAKING CORNER FREQUENCIES 0X0D[7:4] VALUE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF ZERO CORNER FREQUENCY Peaking disabled 800MHz 400MHz 265MHz 200MHz 160MHz 135MHz 115MHz 100MHz 90MHz 80MHz 70MHz 65MHz 60MHz 55MHz 50MHz
Automatic Black Level Compensation (ABLCTM)
ABLC is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the ADC and servoing the 10 bit analog DAC to force those errors to zero. When ABLC is enabled, the user offset control is a digital adder, with 8 bit resolution (See Table 5). When the ABLC function is enabled (0x17[0]=0), the ABLC function is executed every line after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the ABLC function will not be triggered while the DPLL is coasting, preventing any composite sync edges, equalization pulses, or Macrovision signals from corrupting the black data and potentially adding a small error in the ABLC accumulator. After the trailing edge of HSYNC, the start of ABLC is delayed by the number of pixels specified in registers 0x14 and 0x15. After that delay, the number of pixels specified by register 0x17[3:2] are averaged together and added to the ABLC's accumulator. The accumulator stores the average black levels for the number of lines specified by register 0x17[6:4], which is then used to generate a 10 bit DAC value. The default values provide excellent results with offset stability and absolute accuracy better than 1 ADC LSB for most input signals. Increasing the ABLC pixel width or the ABLC bandwidth settings decreases the ABLC's absolute DC error further.
ADC
The X98027 features 3 fully differential, 275MSPS 8 bit ADCs.
Offset DAC
The X98027 features a 10 bit Digital-to-Analog Converter (DAC) to provide extremely fine control over the full channel offset. The DAC is placed after the PGA to eliminate
19
FN8221.0 May 26, 2005
X98027
TABLE 5. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT OFFSET DAC RANGE 0x0C[0] 0 1 0 1 10 BIT OFFSET DAC RESOLUTION 0.25 ADC LSBs (0.68mV) 0.125 ADC LSBs (0.34mV) 0.25 ADC LSBs (0.68mV) 0.125 ADC LSBs (0.34mV) USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09 - 0x0B ONLY (8 BIT OFFSET CONTROL) 1 ADC LSB (digital offset control) 1 ADC LSB (digital offset control) 1.0 ADC LSB (analog offset control) 0.5 ADC LSB (analog offset control) USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09 - 0x0B AND 0x0C[7:2] (10 BIT OFFSET CONTROL) N/A N/A 0.25 ADC LSB (analog offset control) 0.125 ADC LSB (analog offset control)
ABLCTM 0x17[0] 0 (ABLC on) 0 (ABLC on) 1 (ABLC off) 1 (ABLC off)
Clock Generation
A Digital Phase Lock Loop (DPLL) is employed to generate the pixel clock frequency. The HSYNC input and the external XTAL provide a reference frequency to the PLL. The PLL then generates the pixel clock frequency that is equal to the incoming HSYNC frequency times the HTOTAL value programmed into registers 0x0E and 0x0F. The stability of the clock is very important and correlates directly with the quality of the image. During each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. At higher frequencies, the pixel time transitions at a faster rate, which makes the stable pixel time even smaller. Any jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately.
SOG Slicer
The SOG input has programmable threshold, 40mV of hysteresis, and an optional low pass filter than can be used to remove high frequency video spikes (generated by overzealous video peaking in a DVD player, for example) that can cause false SOG triggers. The SOG threshold sets the comparator threshold relative to the sync tip (the bottom of the SOG pulse). A good default SOG slicer threshold setting is 0x16 (hysteresis and low pass filter enabled, threshold lowered slightly to accommodate weak sync tips).
SYNC Status and Polarity Detection
The SYNC Status register (0x01) and the SYNC Polarity register (0x02) continuously monitor all 6 sync inputs (VSYNCIN, HSYNCIN, and SOGIN for each of 2 channels) and report their status. However, accurate sync activity detection is always a challenge. Noise and repetitive video patterns on the Green channel may look like SOG activity when there actually is no SOG signal, while non-standard SOG signals and trilevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected. As a consequence, not all of the activity detect bits in the X980xx are correct under all conditions. Table 6 shows how to use the SYNC Status register (0x01) to identify the presence of and type of a sync source. The firmware should go through the table in the order shown, stopping at the first entry that matches the activity indicators in the SYNC Status register. Final validation of composite sync sources (SOG or Composite sync on HSYNC) should be done by setting the Input Configuration register (0x05) to the composite sync source determined by this table, and confirming that the CSYNC detect bit is set. The accuracy of the Trilevel Sync detect bit can be increased by multiple reads of the Trilevel Sync detect bit. See the Trilevel Sync Detect section for more details. For best SOG operation, the SOG low pass filter (register 0x04[4]) should always be enabled to reject the high frequency peaking often seen on video signals.
Sampling Phase
The X98027 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x10.
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mV steps with 240mV of hysteresis, and a subsequent digital glitch filter that ignores any HSYNC transitions within 100ns of the initial transition. This processing greatly increases the AFE's rejection of ringing and reflections on the HSYNC line and allows the AFE to perform well even with pathological HSYNC signals. Voltages given above and in the HSYNC Slicer register description are with respect to a 3.3V sync signal at the HSYNCIN input pin. To achieve 5V compatibility, a 680 series resistor should be placed between the HSYNC source and the HSYNCIN input pin. Relative to a 5V input, the hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer step size will be 400mV*5V/3.3V = 600mV per step. The best HSYNC slicer threshold is generally 800mV (001b) when locking on the rising edge of an HSYNC signal, or 2.4V (110b) when locking on the falling edge. 20
FN8221.0 May 26, 2005
X98027
TABLE 6. SYNC SOURCE DETECTION TABLE HSYNC DETECT 1 1 0 VSYNC DETECT 1 0 0 SOG DETECT X X 1 TRILEVEL DETECT X X 0 Sync is on HSYNC and VSYNC Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on HSYNC and confirm that CSYNC detect bit is set. Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude is too low to set trilevel detect bit. Use video mode table to determine if this video mode is likely to have trilevel sync, and set clamp start, width values appropriately if it is. Sync is composite sync on SOG. Sync is likely to be trilevel. No valid sync sources on any input. RESULT
0 0
0 0
1 0
1 X
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the SOG activity bit is also set.
Detect should only be considered valid if HSYNC Activity Detect = 0 and SOG Activity Detect = 1. If there is a SOG signal, the TriLevel Detect bit will operate correctly for standard trilevel sync levels (600mVp-p). In some real-world situations, the peak-to-peak sync amplitude may be significantly smaller, sometimes 300mVp-p or less. In these cases the sync slicer will continue to operate correctly, but the TriLevel Detect bit may not be set. Trilevel detection accuracy can be enhanced by polling the trilevel bit multiple times. If HSYNC is inactive, SOG is present, and the TriLevel Sync Detect bit is read as a 1, there is a high likelihood there is trilevel sync.
SOG Activity Detect
The SOG activity detect bit monitors the output of the SOG slicer, looking for 64 consecutive pulses with the same period and duty cycle. If there is no signal on the Green (or Y) channel, the SOG slicer will clamp the video to a DC level and will reject any sporadic noise. There should be no false positive SOG detects if there is no video on Green (or Y). If there is video on Green (or Y) with no valid SOG signal, the SOG activity detect bit may sometimes report false positives (it will detect SOG when no SOG is actually present). This is due to the presence of video with a repetitive pattern that creates a waveform similar to SOG. For example, the desktop of a PC operating system is black during the front porch, horizontal sync, and back porch, then increases to a larger value for the visible portion of the screen. This creates a repetitive video waveform very similar to SOG that may falsely trigger the SOG Activity detect bit. However, in these cases where there is active video without SOG, the SYNC information will be provided either as separate H and V sync on HSYNCIN and VSYNCIN, or composite sync on HSYNCIN. HSYNCIN and VSYNCIN should therefore be used to qualify SOG. The SOG Active bit should only be considered valid if HSYNC Activity Detect = 0. Note: Some pattern generators can output HSYNC and SOG simultaneously, in which case both the HSYNC and the SOG activity bits will be set, and valid. Even in this case, however, the monitor should still choose HSYNC over SOG.
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or SOG) is selected through bits 3 and 4 of register 0x05, the CSYNC Present bit in register 0x01 should be set. CSYNC Present detects the presence of a low frequency, repetitive signal inside HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source.
SYNC Output Signals
The X98027 has 2 pairs of HSYNC and VSYNC output signals, HSYNCOUT and VSYNCOUT, and HSOUT and VSOUT. HSYNCOUT and VSYNCOUT are buffered versions of the incoming sync signals; no synchronization is done. These signals should be used for mode detection. HSOUT and VSOUT are generated by the X98027's logic and are synchronized to the output DATACLK and the digital pixel data on the output databus. HSOUT is used to signal the start of a new line of digital data. VSOUT is not needed in most applications. Both HSYNCOUT and VSYNCOUT (including the sync separator function) remain active in power-down mode. This allows them to be used in conjunction with the Sync Status registers to detect valid video without powering up the X98027.
TriLevel Sync Detect
Unlike SOG detect, the TriLevel Sync detect function does not check for 64 consecutive trilevel pulses in a row, and is therefore less robust than the SOG detect function. It will report false positives for SOG-less video for the same reasons the SOG activity detect does, and should therefore be qualified with both HSYNC and SOG. TriLevel Sync
21
FN8221.0 May 26, 2005
X98027
HSYNCOUT
HSYNCOUT is an unmodified, buffered version of the incoming HSYNCIN or SOGIN signal of the selected channel, with the incoming signal's period, polarity, and width to aid in mode detection. HSYNCOUT will be the same format as the incoming sync signal: either horizontal or composite sync. If a SOG input is selected, HSYNCOUT will output the entire SOG signal, including the VSYNC portion, pre-/post-equalization pulses if present, and Macrovision pulses if present. HSYNCOUT remains active when the X98027 is in power-down mode. HSYNCOUT is generally used for mode detection.
REGISTER 0x19 VALUE 0 1 2 3 4 5 6 7 TABLE 7. HSOUT WIDTH HSOUT WIDTH (PIXEL CLOCKS) 24 BIT MODE, RGB 0 1 2 3 4 5 6 7 24 BIT MODE, YUV 1 1 3 3 5 5 7 7 ALL 48 BIT MODES 0 0 2 2 4 4 6 6
VSYNCOUT
VSYNCOUT is an unmodified, buffered version of the incoming VSYNCIN signal of the selected channel, with the original VSYNC period, polarity, and width to aid in mode detection. If a SOG input is selected, this signal will output the VSYNC signal extracted by the X98027's sync slicer. Extracted VSYNC will be the width of the embedded VSYNC pulse plus pre- and post-equalization pulses (if present). Macrovision pulses from an NTSC DVD source will lengthen the width of the VSYNC pulse. Macrovision pulses from other sources (PAL DVD or videotape) may appear as a second VSYNC pulse encompassing the width of the Macrovision. See the Macrovision section for more information. VSYNCOUT (including the sync separator function) remains active in power-down mode. VSYNCOUT is generally used for mode detection, start of field detection, and even/odd field detection.
VSOUT
VSOUT is generated by the X98027's control logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. Its leading and trailing edges are aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its width, in units of lines, is equal to the width of the incoming VSYNC (see the VSYNCOUT description). Its polarity is determined by register 0x18[6]. This output is not needed in most applications.
Macrovision
The X98027 will synchronize to and digitize Macrovisionencoded YUV video if the source is an NTSC DVD. Macrovision from PAL DVD, or from all video tape sources, is incompatible with the sync slicer, requiring that the Macrovision pulses either be stripped from the video prior to the SOGIN input, or an external COAST signal be generated and applied to the CLKINV pin that will coast the X98027's PLL during the VSYNC and Macrovision period.
HSOUT
HSOUT is generated by the X98027's control logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. Its trailing edge is aligned with pixel 0. Its width, in units of pixels, is determined by register 0x19, and its polarity is determined by register 0x18[7]. As the width is increased, the trailing edge stays aligned with pixel 0, while the leading edge is moved backwards in time relative to pixel 0. HSOUT is used by the scaler to signal the start of a new line of pixels. The HSOUT Width register (0x19) controls the width of the HSOUT pulse. The pulse width is nominally 1 pixel clock period times the value in this register. In the 48 bit output mode (register 0x18[0] = 1), or the YUV input mode (register 0x05[2] = 1), the HSOUT width is incremented in 2 pixel clock (1 DATACLK) increments (see Table 7).
Standby Mode
The X98027 can be placed into a low power standby mode by writing a 0x0F to register 0x1B, powering down the triple ADCs, the DPLL, and most of the internal clocks. To allow input monitoring and mode detection during powerdown, the following blocks remain active: * Serial interface (including the crystal oscillator) to enable register read/write activity * Activity and polarity detect functions (registers 0x01 and 0x02) * The HSYNCOUT and VSYNCOUT pins (for mode detection)
22
FN8221.0 May 26, 2005
X98027
HSYNCIN (to A and B) Analog Video In (to A and B) DATACLK (A) DATA (A) DN-3 DN-1 D0 D2
DPLL Lock Edge
PN-3 PN-2 PN-1 PN P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11 P12
HSOUT (A)
CLKINVIN (A) = GNDD
1/2 DATACLK Delay
DATACLK (B) DATA (B)
DN-2
DN
D1
D3
HSOUT (B)
CLKINVIN (B) = VD
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
Crystal Oscillator
An external 23MHz to 27MHz crystal supplies the low-jitter reference clock to the DPLL. The absolute frequency of this crystal within this range is unimportant, as is the crystal's temperature coefficient, allowing use of less expensive, lower-grade crystals. See Table 8 for additional crystal considerations.
If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler's setup and hold timing requirements continue to be met.
Alternate Pixel Sampling
Two X98027s (AFEA and AFEB) may be used simultaneously to achieve effective sample rates greater than 275MHz. Each AFE is programmed with an HTOTAL value equal to one-half of the total number of pixels in a line. The CLOCKINVIN pin for AFEA is tied to ground, AFEB is tied to VD. Both AFEs are otherwise programmed identically, though some minor phase adjustment may be needed to compensate for any propagation delay mismatch between the two AFEs. The CLOCKINVIN setting shifts the phase of AFEB by 180 degrees from AFEA. AFEA now samples the even pixels on the rising edge of its DATACLK, while AFEB samples the odd pixels on the rising edge of its clock. With each AFE in 24 bit mode, two 24 bit data streams are generated (Figure 9). With both AFEs configured for 48 bit mode, a 96 bit datastream is generated (Figure 10). In both cases, AFEA and AFEB are on different DATACLK domains. In 24 bit mode, the data from each AFE must be latched on the rising edge of that AFE's DATACLK. In 48 bit mode, the frequencies are low enough that the rising edge of AFE B can be used to capture both AFEB and AFEA data.
EMI Considerations
There are two possible sources of EMI on the X98027: * Crystal oscillator. The EMI from the crystal oscillator is negligible. This is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. The crystal oscillator is not a significant source of EMI. * Digital output switching. This is the largest potential source of EMI. However, the EMI is determined by the PCB+ layout and the loading on the databus. The way to control this is to put series resistors on the output of all the digital pins. These resistor values should be adjusted to optimize signal quality on the bus. Intersil recommends starting with 22 and adjusting as necessary for the particular PCB layout and device loading. Recommendations for minimizing EMI are: * Minimize the databus trace length * Minimize the databus capacitive loading.
23
FN8221.0 May 26, 2005
X98027
HSYNCIN (to A and B) Analog Video In (to A and B) PIXELCLK (A) (Internal) DATACLK (A)
DPLL Lock Edge
PN-3 PN-2 PN-1 PN P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11 P12
DATAPRI (A) DATASEC (A) HSOUT (A)
DN-3 DN-1
D0 D2
CLKINVIN (A) = GNDD
1/2 PIXELCLK = 1/4 DATACLK Delay
PIXELCLK (B) (Internal) DATACLK (B)
DATAPRI (B) DATASEC (B) HSOUT (B)
DN-2 DN
D1 D3
CLKINVIN (B) = GNDD
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
Initialization
.
The X98027 initializes with default register settings for an AC-coupled, RGB input on the VGA1 channel, with a 24 bit output. The following registers should be written to fully enable the chip: * Register 0x1C should be set to 0x49 to improve DPLL performance in video modes * Register 0x23 should be set to 0x78 to enable the DC Restore function * Write the correct crystal compensation value to Register 0x2B (see below).
Internal Clock Frequency The internal clock frequencies need to be tightly controlled to minimize power consumption. Register 0x2B should be set to 1 + the integer portion of (2*fPIXELCLOCKMAX/fCRYSTAL). For example, if the maximum pixel clock is 263MHz, and the crystal frequency is 24MHz, then register 0x2B should be set to 1 + INT(2*263/24) = 1 + INT(21.917) = 1 + 21 = 22 = 0x16. The following table illustrates the compensation values required to operate the X98027 at its maximum speed of 275MHz. If lower maximum Pixel Clock frequencies are needed, using the formula above will minimize power consumption.
Power Dissipation at QXGA Speeds
Because of the very high speed of the X98027, power consumption is a concern. There are several things that can be done to reduce power consumption:
24
FN8221.0 May 26, 2005
X98027
TABLE 8. X98027 CRYSTAL COMPENSATION CRYSTAL FREQUENCY RANGE (MHz) 23 - 23.9 23.9 - 25 25.0 - 26.2 26.2 - 27 REGISTER 0x2B VALUE VALUE (DECIMAL) 24 23 22 21 HEX 0x18 0x17 0x16 0x15
Conditions required: negative polarity VSYNC, with no serrations, and t1 = t2 t1 t2
HSYNCIN
FIGURE 11. CSYNC ON HSYNC THAT MAY CAUSE SPORADIC IMAGE SHIFTS
Internal Voltage Regulator The X98027 features a 3.3V to 1.9V voltage regulator (pins 64 and 65). This regulator typically sources up to 100mA at 1.9V, dissipating up to 140mW in heat. Providing an external, clean 1.8V supply to the VCORE, VPLL, and VCOREADC will substantially reduce power dissipation
This only happens with the exact waveshape shown in Figure 11. If the polarity of the sync signal is inverted from that shown in Figure 11, the problem will not occur. If there are any serrations during the VSYNC period, the problem will not occur. The problem also will not occur if the sync signal is on the SOG input. This is a rarely used composite sync format; in most applications it will never be encountered. However if this CSYNC waveform must be supported, there is a simple applications solution using an XOR gate. The output of the XOR gate is connected to the HSYNCIN input of the X98027. One of the XOR inputs is connected to the HSYNC/CSYNC source, and the other input is connected to a general purpose I/O. For all sync sources except the CSYNC shown in Figure 11, the input connected to the GPIO should be driven low. If the system microcontroller detects a mode corresponding to the sync type and polarity shown in Figure 11, it should drive the GPIO pin high. This will invert the CSYNC signal seen by the X98027 and prevent any spontaneous image shifting.
* Buffering Digital Outputs Switching 48 DATA OUTPUT bits at a 275MHz/2 rate consumes a lot of current. The higher the capacitance on the external databus, the higher the switching current. To minimize current consumption inside the X98027, data buffers such as the SN64AVC16827 should be placed between the X98027's data outputs and the external databus. For bus capacitances of 15pF or lower, this is highly recommended. For bus capacitances greater than 15pF, this is mandatory!
Reset
The X98027 has a Power-On Reset (POR) function that resets the chip to its default state when power is initially applied, including resetting all the registers to their default settings as described in the Register Listing. The external RESET pin duplicates the reset function of the POR without having to cycle the power supplies. The RESET pin does not need to be used in normal operation and can be tied high.
X98027 Serial Communication
Overview
The X98027 uses a 2 wire serial bus for communication with its host. SCL is the Serial Clock line, driven by the host, and SDA is the Serial Data line, which can be driven by all devices on the bus. SDA is open drain to allow multiple devices to share the same bus simultaneously.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator function. If the CSYNC signal shown in Figure 11 is present on the HSYNC input, and the sync source is set to CSYNC on HSYNC, HSOUT may sporadically lock to the wrong edge of HSYNCIN. This will cause the HSOUT to have the wrong position relative to pixel 0, resulting in the image shifting left or right by the width of the HSYNCIN signal for about 1 second before it corrects itself.
25
FN8221.0 May 26, 2005
X98027
Communication is accomplished in three steps: 1. The Host selects the X98027 it wishes to communicate with. 2. The Host writes the initial X98027 Configuration Register address it wishes to write to or read from. 3. The Host writes to or reads from the X98027's Configuration Register. The X98027's internal address pointer auto increments, so to read registers 0x00 through 0x1B, for example, one would write 0x00 in step 2, then repeat step 3 28 times, with each read returning the next register value. The X98027 has a 7 bit address on the serial bus. The upper 6 bits are permanently set to 100110, with the lower bit determined by the state of pin 48. This allows 2 X98027s to be independently controlled while sharing the same bus. The bus is nominally inactive, with SDA and SCL high. Communication begins when the host issues a START command by taking SDA low while SCL is high (Figure 12). The X98027 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. The host then transmits the 7 bit serial address plus a R/W bit, indicating if the next transaction will be a Read (R/W = 1) or a Write (R/W = 0). If the address transmitted matches that of any device on the bus, that device must respond with an ACKNOWLEDGE (Figure 13). Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a STOP command, where SDA rises while SCL is high (Figure 12), or a second START command, which is commonly used to reverse data direction without relinquishing the bus. Data on the serial bus must be valid for the entire time SCL is high (Figure 14). To achieve this, data being written to the X98027 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the X98027 for 3 crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication. When the contents of the X98027 are being read, the SDA line is updated after the falling edge of SCL, delayed and deglitched in the same manner.
Configuration Register Write
Figure 15 shows two views of the steps necessary to write one or more words to the Configuration Register.
Configuration Register Read
Figure 16 shows two views of the steps necessary to read one or more words from the Configuration Register.
SCL
SDA Start Stop
FIGURE 12. VALID START AND STOP CONDITIONS
SCL from Host Data Output from Transmitter Data Output from Receiver Start
1
8
9
Acknowledge
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
26
FN8221.0 May 26, 2005
X98027
SCL
SDA Data Stable Data Change Data Stable
FIGURE 14. VALID DATA CHANGES ON THE SDA BUS
START Command X98027 Serial Bus Address 1 0 0 1 1 0 A (pin 48) R/W 0
Signals the beginning of serial I/O X98027 Serial Bus Address Write This is the 7 bit address of the X98027 on the 2 wire bus. The address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. Shift this value to left when adding the R/W bit X98027 Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0
This is the address of the X98027's configuration register that the following byte will be written to. X98027 Register Data Write(s) This is the data to be written to the X98027's configuration register. Note: The X98027's Configuration Register's address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the Configuration Register. Signals the ending of serial I/O S T O P A C K
D7
D6
D5
D4
D3
D2
D1
D0
(Repeat if desired)
STOP Command S T Serial Bus A R Address T 1 0 0 1 1 0A0 A C K Register Address aaaaaaaa A C K Data Write* dddddddd
Signals from the Host SDA Bus Signals from the X98027
* The data write step may be repeated to write to the X98027's Configuration Register sequentially, beginning at the Register Address written in the previous step.
FIGURE 15. CONFIGURATION REGISTER WRITE
27
FN8221.0 May 26, 2005
X98027
Signals the beginning of serial I/O R/W 0 A (pin 48) 0 X98027 Serial Bus Address Write This is the 7 bit address of the X98027 on the 2 wire bus. The address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 0, indicating next transaction will be a write. X98027 Register Address Write A7 A6 A5 A4 A3 A2 A1 A0 This sets the initial address of the X98027's configuration register for subsequent reading Ends the previous transaction and starts a new one X98027 Serial Bus Address Write This is the 7 bit address of the X98027 on the 2 wire bus. The address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 1, indicating next transaction(s) will be a read. X98027 Register Data Read(s) This is the data read from the X98027's configuration register. Note: The X98027's Configuration Register's address pointer auto increments after each data read: repeat this step to read multiple sequential bytes of data from the Configuration Register. Signals the ending of serial I/O R E S T Serial Bus A Address R T 1 0 0 1 1 0A1 A C K
START Command X98027 Serial Bus Address 1 0 0 1 1
START Command X98027 Serial Bus Address 1 0 0 1 1 0 A (pin 48) D2 D1 D0 R/W 1
D7
D6
D5
D4
D3
(Repeat if desired)
STOP Command S T Serial Bus A R Address T 1 0 0 1 1 0A0 A C K
Signals from the Host
Register Address aaaaaaaa
Data Read*
SDA Bus Signals from the X98027
S T O AP C K
* The data read step may be repeated to read from the X98027's Configuration Register sequentially, beginning at the Register Address written in the two steps previous.
Adddddddd C K
FIGURE 16. CONFIGURATION REGISTER READ
28
FN8221.0 May 26, 2005
X98027 128-Lead Metric Quad Flat Pack (MQFP) Package Type L
All dimensions in mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
29
FN8221.0 May 26, 2005

▲Up To Search▲

Price & Availability of X98027L128-33-Z

	To Download X98027L128-33-Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .